1. Technical Field
The subject matter described herein relates to communication systems, and in particular, to techniques for mitigating spurs.
2. Background Art
A fractional phase-locked loop (PLL) is used in many wireless solutions and is present to generate all of the channelization transmit/receive frequencies with sufficient granularity per various standards. Typically, a fractional PLL is configured to multiply a reference frequency by a factor of (N+f), where N is an integer number, and f is a fractional ratio (i.e., 0<f<1). With sufficient resolution in factor f, any arbitrary frequency can be generated. Unfortunately, fractional PLL implementations suffer from the presence of a relatively strong fractional spur at distance D of the nominal tone frequency, where D is equal to f multiplied by the reference frequency.
This fractional spur may be created by several different mechanisms such as non-linear coupling of the Nth harmonic in the reference frequency and the output frequency of the clock signal provided by the fractional PLL, delta-sigma quantization noise, coupling/leakage, etc. Many of these spur sources are becoming exceedingly difficult or inefficient to mitigate in the analog domain given the tighter requirements of the latest protocols used in communication systems. Some analog-domain mitigation techniques require better isolations of particular circuitry of the fractional PLL (e.g., the voltage control oscillator), thereby requiring a larger area for implementation. Other analog-domain mitigation techniques require a large amount of current or higher supply voltages.
Accordingly, even with the deployment of known analog-domain optimization/mitigation methods, meeting the stringent spur-level requirements for next generation communication systems is proving to be unreliable and inefficient.